1. Field of the Invention
This invention relates generally to techniques for implementing memory systems, and relates more particularly to a system and method for effectively implementing a high-speed DRAM device.
2. Description of the Background Art
Implementing effective methods for implementing memory systems is a significant consideration for designers and manufacturers of contemporary electronic entertainment systems. However, effectively implementing memory systems may create substantial challenges for system designers. For example, enhanced demands for increased system functionality and performance may require more system memory and require additional hardware resources. An increase in memory or related hardware requirements may also result in a corresponding detrimental economic impact due to increased production costs and operational inefficiencies.
Furthermore, enhanced system capability to perform various advanced operations may provide additional benefits to a system user, but may also place increased demands on the control and management of system memory devices. For example, an enhanced electronic system that effectively supports interactive television may benefit from an efficient memory implementation because of the large amount and complexity of the digital data involved.
Due to growing demands on system resources and substantially increasing data magnitudes, it is apparent that developing new techniques for implementing and utilizing memory systems is a matter of concern for related electronic technologies. Therefore, for all the foregoing reasons, developing effective systems for implementing and utilizing memory devices remains a significant consideration for designers, manufacturers, and users of contemporary electronic systems.
In accordance with the present invention, a system and method are disclosed for effectively implementing a high-speed DRAM device for performing various accelerated-write operations. In accordance with one embodiment of the present invention, initially, a DRAM controller or other appropriate entity may activate a wordline corresponding to a DRAM cell in the DRAM device to thereby initiate a corresponding accelerated-write operation.
Immediately after the foregoing wordline is turned on, in accordance with the present invention, bitline voltage levels for a bitline and a corresponding bitline bar may begin to diverge in opposite directions in an accelerated bitline split/amplification procedure. In addition, the bitline and bitline bar may preferably begin to diverge towards pre-toggled states that correspond to final state levels of the accelerated-write operation.
In response to the foregoing change in bitline voltage levels, a cell voltage level representing a stored data value in the DRAM cell may immediately start to charge or discharge, depending upon whether the accelerated-write operation is a low-to-high transition (charge) or a high-to-low transition (discharge). Then, a sense amplifier may be enabled for amplifying the bitline voltage levels to reach their respective bitline full-state levels.
Next, in accordance with the present invention, the foregoing cell voltage level of the DRAM cell may advantageously reach a cell voltage full-state level before termination of the high-speed memory cycle. The DRAM controller or other entity may subsequently de-activate the wordline to the DRAM cell to store the corresponding write-data value. Finally, a sense amplifier or other appropriate entity may equalize the bitline voltage levels for the bitline and the bitline bar to prepare the DRAM cell for another high-speed memory access cycle. The present invention thus provides an effective system and methodology for implementing a high-speed DRAM device that performs an accelerated-write operation.